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Unread postPosted: Wed Dec 02, 2009 2:12 pm 
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this would make a cool processor to base a future rackable* product on. i assume the memory channel would not be too crippling...

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http://news.cnet.com/8301-30685_3-10407818-264.html

from now on, in my mind, if it isn't ccnuma; it's rackable.

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Unread postPosted: Thu Dec 03, 2009 9:35 am 
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Coolthreads anyone...? :p

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Unread postPosted: Thu Dec 03, 2009 10:43 am 
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From what I see so far, this isn't that exciting. If its an Atom derivative, as many are speculating, that means its 32-bit... and who knows what this thing's floating-point and/or SIMD capabilities are. Also, doesn't using pure message-passing instead of cache coherence have problems?

I don't see anything here as exciting as, for instance, Tilera's chips.

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Unread postPosted: Thu Dec 03, 2009 12:50 pm 
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Tilera's look interesting too. different solutions for different problems. octane III has a "tons of atom's" option too.

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Unread postPosted: Thu Dec 03, 2009 4:54 pm 
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If they solve the memory contention issue it'll start to look like a small Connection Machine with slightly more powerful nodes.

The more things change...

[edit] Correction - it won't. It appears to just be either a SMP/semi-NUMA type of configuration of a whole bunch of low-end processors or a cluster-on-a-chip.

A CM-2 successor on a chip would be a neat device, though, and this is halfway there...

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Last edited by SAQ on Sun Dec 06, 2009 9:37 am, edited 2 times in total.

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Unread postPosted: Thu Dec 03, 2009 5:20 pm 
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Rhys wrote:
From what I see so far, this isn't that exciting. If its an Atom derivative, as many are speculating, that means its 32-bit... and who knows what this thing's floating-point and/or SIMD capabilities are. Also, doesn't using pure message-passing instead of cache coherence have problems?

I don't see anything here as exciting as, for instance, Tilera's chips.


How does atom-derivative and 32-bit go together? I have two Atom-based mother boards right here, both are 64-bit capable. In fact, let me show you on my D945GCLF2 board, running Solaris, dual-core Atom w/HT:

Code:
tiny:~$ isainfo -kv
64-bit amd64 kernel modules

tiny:~$ isainfo -bv
64-bit amd64 applications
        ssse3 cx16 mon sse3 pause sse2 sse fxsr mmx cmov amd_sysc cx8 tsc fpu

tiny:~$ psrinfo -v
Status of virtual processor 0 as of: 12/03/2009 17:16:44
  on-line since 11/08/2009 23:48:56.
  The i386 processor operates at 1600 MHz,
        and has an i387 compatible floating point processor.
Status of virtual processor 1 as of: 12/03/2009 17:16:44
  on-line since 11/08/2009 23:48:59.
  The i386 processor operates at 1600 MHz,
        and has an i387 compatible floating point processor.
Status of virtual processor 2 as of: 12/03/2009 17:16:44
  on-line since 11/08/2009 23:48:59.
  The i386 processor operates at 1600 MHz,
        and has an i387 compatible floating point processor.
Status of virtual processor 3 as of: 12/03/2009 17:16:44
  on-line since 11/08/2009 23:48:59.
  The i386 processor operates at 1600 MHz,
        and has an i387 compatible floating point processor.

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Unread postPosted: Fri Dec 04, 2009 7:12 am 
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The desktop-targeted Atoms are 64-bit, however the most commonly used ones (N270 and relatives) are not. The article says "lower-end Atom processors," which I assumed specifically meant the lower-end processors from the Atom line. I could be horribly wrong, and it could be calling all Atoms "lower-end." Who knows.

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Unread postPosted: Fri Dec 04, 2009 10:25 am 
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Rhys wrote:
The article says "lower-end Atom processors," which I assumed specifically meant the lower-end processors from the Atom line.


Well I'll admit I didn't read the article before posting. I think they were calling the entire line lower-end. Besides, 64-bits comes in handy when you need to address the 64 GB max memory they claimed in the article.

Might be handy to have a little more memory, 1.333 gb/core is a little small.

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Unread postPosted: Fri Dec 04, 2009 9:31 pm 
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japes wrote:
Well I'll admit I didn't read the article before posting. I think they were calling the entire line lower-end. Besides, 64-bits comes in handy when you need to address the 64 GB max memory they claimed in the article.

There was an article in the Inquirer ages ago about a 'sperimental SGI computer running hundreds ot Atom processors. This was back before the buyout ... Sounded interesting then, nice that it didn't die.

There's also some small place selling 8 and 16 core MIPS processors and mainboards for them for servers. Maybe it's time to re-animate that old argument with R-10 about how no one but Intel is big enough to develop processors these days :P

SGI, that powerhouse of imagination, coulda woulda shoulda. Where's that horse again ?


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Unread postPosted: Sat Dec 05, 2009 9:29 am 
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@Hamei: Are you referring to RMI Corporation? The XLP has 8 cores, 4 threads each at 2GHz. They just got bought out though, so we'll see if that all goes down the drain.

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Unread postPosted: Sun Dec 06, 2009 9:44 am 
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Now I'm confused. Originally I thought this was something that it wasn't, and now I'm still not completely sure after looking at the Intel stuff.

Is this a single-chip implementation of a massively parallel computer (such as the Cray T3) using lower end processors and interconnects that bring down latency, or is this something different? Is it designed to be used alone, used with a master processor (more in the Connection Machine style) or both? Or is this just a slightly improved Beowulf on a chip? (I know that Beowulf is a variant of massively parallel processing, but Beowulf:T3E is roughly like quad PPro:Challenge L. Some similarities, but not in the same league.

How is the memory attached?

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Unread postPosted: Sun Dec 06, 2009 1:45 pm 
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24 dual core atom-power processor with a 64GB/sec interconnect to one of four memory controllers that can address a total of 64GB of ram.

i wouldn't associate it with previous architectures as much as the natural evolution of x86 processors that have hit the useful clock frequency barrier. time to scale out rather than scale up as it were - adding more moderate clock rate cores/processors/threads to gain performance.

from now on the software really has to get smarter rather than just bloated :) at least as long as we're stuck with cmos.

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