PMC RM7000C-600T CPUs on ebay

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mattst88
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Re: PMC RM7000C-600T CPUs on ebay

Unread postby mattst88 » Thu Oct 29, 2009 11:29 am

mapesdhs wrote:rumble writes:
> Lack of PROM source probably isn't the problem so much as the inability to alter the IRIX kernel is.

Nope, according to Joe, we DO need the PROM source.


I don't think he's claiming it's unneeded, just that the IRIX kernel poses a larger problem.

mapesdhs wrote:> think it'd be reasonably straightforward to create a workable replacement that could load a Linux or BSD kernel.

Who the heck cares about Linux or BSD on O2? IRIX rules on this system. Otherwise, it's just a generic box. *yawn*


I do, but this is really a different topic.
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Re: PMC RM7000C-600T CPUs on ebay

Unread postby rumble » Sat Oct 31, 2009 1:50 pm

bri3d wrote:An IRIX kernel wouldn't need alteration to run with a custom bootloader - once you've got the hard part (bringup) done I am fairly sure loading sash is a matter of read and jump.


The problem is that the kernel is likely not to work for the exact same reasons the PROM won't. Why should we expect the IRIX IP32 kernel to know how to deal with the peculiarities of the new core if the PROM doesn't? In fact, I imagine there's more room for concern as the PROM uses far less CPU functionality than the kernel does.

bri3d wrote:CPU/bus/co-processor bringup (the part we'd need to change) would be the challenge - to the best of my knowledge, no open-source code can do it - we have knowledge of how to bit-bang the hardware once it's up, from Linux and NetBSD folks, but I don't think anyone's worked out how to bring it up at the low level. Considering the wide variety of goofy hardware inside the O2, I think bringup might get pretty involved.


That's why we run it in gxemul and see what it does. I'm guessing this part isn't quite as difficult as you imagine.

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Re: PMC RM7000C-600T CPUs on ebay

Unread postby rumble » Sat Oct 31, 2009 1:57 pm

mapesdhs wrote:rumble writes:
> Lack of PROM source probably isn't the problem so much as the inability to alter the IRIX kernel is.

Nope, according to Joe, we DO need the PROM source.


And I'm saying that we do not. Why would we if we could roll our own? I'm not convinced by unsubstantiated appeals to authority.

mapesdhs wrote:> think it'd be reasonably straightforward to create a workable replacement that could load a Linux or BSD kernel.

Who the heck cares about Linux or BSD on O2? IRIX rules on this system. Otherwise, it's just a generic box. *yawn*

> ... but you can kiss running IRIX goodbye.

Boring IMO. More pointless than a fart in a thunderstorm.

Ian.


Opinion. Running IRIX is pretty pointless, too, is it not?

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Re: PMC RM7000C-600T CPUs on ebay

Unread postby kramlq » Sat Oct 31, 2009 3:02 pm

rumble wrote:The problem is that the kernel is likely not to work for the exact same reasons the PROM won't. Why should we expect the IRIX IP32 kernel to know how to deal with the peculiarities of the new core if the PROM doesn't? In fact, I imagine there's more room for concern as the PROM uses far less CPU functionality than the kernel does.


Actually the PROM is likely to be far trickier than the kernel. When PROM on a MIPS CPU gets control at the boot vector, the cache is in a completely undefined state (as is the TLB). So even things like cache line address tags, state and check bits and config registers may have garbage values. It has to completely initialise it to a point so that it is possible to even enable the cache without causing errors. So the PROM is working with the cache hardware at a much closer level. Much of the initialisation is already done by the time a kernel gets control, the idea being that it can then just query the PROM config tree to find out about the cache and just handle normal synchronisation during page mapping changes, DMA etc. While the kernel isn't immune from changes in cache hardware (depending on how it is written obviously), it is less tied to it than the PROM is.

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Re: PMC RM7000C-600T CPUs on ebay

Unread postby rumble » Sun Nov 01, 2009 11:40 am

I see what you mean, but I still don't believe that it would be so difficult. Setting up such state isn't magical (assuming there are docs for the CPU), it's just tedious. Heck, this topic is covered for the R3k in about 20 pages in The MIPS Programmer's Handbook.

My point is simply that the IRIX kernel is very unlikely to support this new core unmodified and that this could well prove a more substantial task than getting around the PROM limitation. Though who knows? Perhaps we'd only need to patch up the Processor ID check somewhere if the cpu is binary compatible with some already existing cache/tlb/etc configuration. Plus, symmon makes debugging much easier.

Anyway, I'm much less pessimistic that this couldn't be done. I messaged ChicagoJoe a year or two ago to inquire about the more recent chips he had soldered, but never heard back. I guess we'll never know.

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Re: PMC RM7000C-600T CPUs on ebay

Unread postby kramlq » Sun Nov 01, 2009 1:39 pm

rumble wrote:I see what you mean, but I still don't believe that it would be so difficult. Setting up such state isn't magical (assuming there are docs for the CPU), it's just tedious.

MIPS isn't the worst of CPUs thankfully, but cache code is quite intricate stuff at times (I've written some). Bugs can be very tough to pinpoint and track down. Of course it mainly depends on how ambitious people may get trying to shoehorn in new CPUs with specs that vary a lot from those originally supported in O2 + IRIX.

And sometimes it does involve magic :lol: Look in Linux from a few years ago and you might find a comment warning people "not to even breathe" on the cache initialisation code (because it was so hard to get right).

rumble wrote:Heck, this topic is covered for the R3k in about 20 pages in The MIPS Programmer's Handbook.

Things evolved a little since the R3k :) I dont have any R3k book anymore, but I think it had physical indexing and tagging, direct mapping and was write through, which was about as simple as cache hardware gets. The RM7k series supports a split onboard L1 cache, joint onboard L2 cache, and off chip L3 cache.

My point is simply that the IRIX kernel is very unlikely to support this new core unmodified and that this could well prove a more substantial task than getting around the PROM limitation. Though who knows? Perhaps we'd only need to patch up the Processor ID check somewhere if the cpu is binary compatible with some already existing cache/tlb/etc configuration. Plus, symmon makes debugging much easier.

Yes. As long as things are kept similar to existing models, then it could be doable. That is probably why the 600MHz model worked so well. But AFAIK the faster CPU's Joe tried were supposed to be binary compatible as well, yet they didn't work.

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Re: PMC RM7000C-600T CPUs on ebay

Unread postby mapesdhs » Sun Nov 01, 2009 2:45 pm

rumble writes:
> And I'm saying that we do not. Why would we if we could roll our own? I'm not convinced by unsubstantiated appeals to authority.

In that case, feel free to try. :D


> Opinion. Running IRIX is pretty pointless, too, is it not?

Blatantly no because that's the only and sensible way to exploit the hardware accelerated and full
functionality of an O2.

Ian.


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