neko_iverilog (Icarus Verilog) uploaded to incoming

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emachine
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Joined: Sun Aug 14, 2005 3:26 pm

neko_iverilog (Icarus Verilog) uploaded to incoming

Unread postby emachine » Sun Jun 22, 2008 10:22 am

What: Icarus Verilog

What is it:
Icarus Verilog is intended to compile ALL of the Verilog HDL as
described in the IEEE-1364 standard. Of course, it's not quite there
yet. It does currently handle a mix of structural and behavioral
constructs. For a view of the current state of Icarus Verilog, see its
home page at <http://www.icarus.com/eda/verilog>.

Icarus Verilog is not aimed at being a simulator in the traditional
sense, but a compiler that generates code employed by back-end
tools. These back-end tools currently include a simulator engine
called VVP, an XNF (Xilinx Netlist Format) generator and an EDIF FPGA
netlist generator. In the future, backends are expected for EDIF/LPM,
structural Verilog, VHDL, etc.


I have successfully compiled and run several Verilog designs / testbenches. Now to start building GTKwave.....

Cheers,
Eric

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