assembly to flush I | D caches

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nyef
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Re: assembly to flush I | D caches

Unread postby nyef » Mon Dec 21, 2015 5:10 pm

See MIPS Run (first edition) says that the R10k has an R4000-style cache, and gives example code. I have no idea at this point if it really is an R4000-style cache or if there's some special trick to it. Presumably the Linux kernel source could be a resource, although if you're looking for code to compare that with for debug purposes then that's just sending you back to your starting point.

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Kumba
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Re: assembly to flush I | D caches

Unread postby Kumba » Thu Jan 07, 2016 3:16 am

ivelegacy wrote:
nyef wrote:See MIPS Run (first edition) says that the R10k has an R4000-style cache


I do not have a copy on hand, I have an hardcover (paper) copy but it's not on hand (250 Km far from where I am) so I am going to buy an ebook for my kindle, this way you always have a copy on hand when you need a lecture, example, or MIPSfun :D

R10K family is an R4K-style cache. In fact, a *lot* of MIPS processors, including many modern-day ones, still have this R4K-style cache layout. If it ain't broke, don't fix it.


ivelegacy wrote:Linux is too bloated, up to 60 Mbyte of sources, I find myself drowning in all their clutter and a bit tired of having to dig through a lot of sources with a lot of #IFDEF to find the article of good source I need!

In the old days, it apparently wasn't too difficult to write assembler that was better than what a compiler can generate. But nowadays, gcc is really, really difficult to beat. So, a lot of the old assembler code that used to power the critical bits of Linux/MIPS code have been replaced by C-equivalents for better readability and maintainability.

That said, yes, certain parts of the Linux tree can be quite a mess (like, why is sound/ at the root instead of under drivers/ ?), but the arch/mips/* folder is pretty well organized:

R4K-cache core code:
http://lxr.free-electrons.com/source/ar ... mm/c-r4k.c

The generic cache interface definitions are here:
http://lxr.free-electrons.com/source/ar ... mm/cache.c

And the relevant header files:
http://lxr.free-electrons.com/source/ar ... sm/cache.h
http://lxr.free-electrons.com/source/ar ... cheflush.h
http://lxr.free-electrons.com/source/ar ... cacheops.h
http://lxr.free-electrons.com/source/ar ... r4kcache.h (this one has templated asm for R4K caches)

Most cache-related and TLB-related code is under the 'mm' directory in the MIPS' arch folder, if you want to look at what other CPUs do. Maybe you'll have better luck than me in reading and understanding it!
:Onyx2: 4x R14000 :Tezro: 4x R16000 :Fuel: 1x R16000 :Octane: 2x R14000 :O2+: RM7000 :O2: R10000 :O2: RM5200 :Indigo: R4400 :Indigo2IMP: R10000 :Indigo2: R8000 :O3x0: 4x R14000 :Indy: R5000

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--Emperor Turhan, Centauri Republic


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