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Boot-Mips - one step closer to a 900 MHz sgi O2

Posted: Sat Apr 23, 2016 4:10 pm
by rwengerter
Approximately a week ago I discovered the PDF document "Boot-MIPS: Example Boot Code for MIPS Cores"
which I needed for developing boot code for an embedded MIPS processor for work.
I did not know that such a detailed PDF document about MIPS boot code exists. It has more than 140 pages and
contains a wealth of information. It applies to all MIPS processors.
Although the older MIPS processors like R10000 and R5000 etc. are not mentioned, it contains information for
the 24K, 74K, 1004K, MicroAptiv etc.

With this PDF document it is possible to put together a tailored boot code for the 900 MHz RM7965A processor from
PMC-Sierra that is suitable as a processor for a hardware-upgrade of a 350 MHZ RM7000 sgi O2 processor module.
This missing boot code is the main reason why the fastest processor upgrade is a 600 MHz RM7xxx processor from
PMC-Sierra.

I guess I now have the missing information to actually start designing a PCB for such a sgi O2 processor module
and use the two RM7965A from my cupboard that are waiting there for several years. The only thing missing is
enough time. :(

I have attached the PDF-document.

Re: Boot-Mips - one step closer to a 900 MHz sgi O2

Posted: Sat Apr 23, 2016 5:08 pm
by robespierre
That document doesn't say anything about Microsemi RM7965A.
The RM7965A data sheet does say:
For memory management support, the E9000 CP0 is logically identical to the CPU cores used in the RM5200 Family and the RM7000 Family.

Which means that initialization is going to be almost identical to RM5200 used in the O2. But of course it isn't going to work unless the PRId is explicitly recognized. You do not need "tailored boot code".

Re: Boot-Mips - one step closer to a 900 MHz sgi O2

Posted: Mon Apr 25, 2016 8:00 pm
by robespierre
You do need a new PCB design, or at least an interposer, because the BGA array is not the same size or layout as the RM5200. And it has no external cache support, so it is not possible to have a L3 cache as the RM7000C upgrade does. If everything else works, you could simply remove the cache chips from the donor board.

Re: Boot-Mips - one step closer to a 900 MHz sgi O2

Posted: Tue Apr 26, 2016 2:15 pm
by rwengerter
robespierre wrote:You do need a new PCB design, or at least an interposer, because the BGA array is not the same size or layout as the RM5200.

I would have made a PCB anyway. The SysAD bus that is used, is well documented.
I would put a current FPGA on the PCB, too. A suitable whitepaper is
"Benefits of using Xilinx FPGAs with MIPS Microprocessors" Link:
http://www.xilinx.com/ipcenter/processor_central/wp121.pdf

This whitepaper shows how to use the SysAD bus with a FPGA.
However, missing time to do such a project would be my biggest
problem,

Re: Boot-Mips - one step closer to a 900 MHz sgi O2

Posted: Wed Aug 23, 2017 6:53 am
by Hombre71
rwengerter wrote:
robespierre wrote:You do need a new PCB design, or at least an interposer, because the BGA array is not the same size or layout as the RM5200.

I would have made a PCB anyway. The SysAD bus that is used, is well documented.
I would put a current FPGA on the PCB, too. A suitable whitepaper is
"Benefits of using Xilinx FPGAs with MIPS Microprocessors" Link:
http://www.xilinx.com/ipcenter/processor_central/wp121.pdf

This whitepaper shows how to use the SysAD bus with a FPGA.
However, missing time to do such a project would be my biggest
problem,


White walker time, this topic has come back from the dead. Just curious if any progress was made? Thanks.

Re: Boot-Mips - one step closer to a 900 MHz sgi O2

Posted: Thu Sep 07, 2017 3:44 pm
by rwengerter
Hombre71 wrote:
rwengerter wrote:
robespierre wrote:You do need a new PCB design, or at least an interposer, because the BGA array is not the same size or layout as the RM5200.

I would have made a PCB anyway. The SysAD bus that is used, is well documented.
I would put a current FPGA on the PCB, too. A suitable whitepaper is
"Benefits of using Xilinx FPGAs with MIPS Microprocessors" Link:
http://www.xilinx.com/ipcenter/processor_central/wp121.pdf

This whitepaper shows how to use the SysAD bus with a FPGA.
However, missing time to do such a project would be my biggest
problem,


White walker time, this topic has come back from the dead. Just curious if any progress was made? Thanks.


I have send an answer to Hombre71 as a private message. The reason is, that special hardware is
required that is less than 100 times available worldwide.