Unix Emulation

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R-ten-K
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Re: Unix Emulation

Unread postby R-ten-K » Mon Nov 03, 2008 10:10 pm

Wow. I did not know they had commercialized simics. I knew one of the students involved when it was an academic project (still is?) back in Norway (or Sweden?). As the previous poster said under most configs, simics used to be slower than molasses. I assume it still is, because the folks at CMU are currently trying to speed up simics (and possibly other full system emulators) by offloading some of the processor emulation and timing models to their version of the ramp HW accelerator (a board with a bunch of FPGAs interconnected). They used to have some public systems running a frontend executing simics, and 16 SPARCS accelerated via FPGAs. It was quite interactive, pretty neat since it is a large multicore system fully emulated (normally you would be lucky to get thousands of instructions emulated per second in an architectural simulation of so many cores, basically a 2 second benchmark would take a day to run).

If you are interested, you can get QEMU to model a full sparcstation (maybe they have included ultras by now) and can boot solaris off it.
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Re: Unix Emulation

Unread postby kramlq » Tue Nov 04, 2008 2:47 am

R-ten-K wrote:LOL we submitted at the same time about SimOS.

From what I read from you about HP-PA it sounds like the architecture is fairly ugly... it would be interesting to find out why the #$#@ they decided to make those privileged ops such a PITA to deal with. The overhead, in instructions, that introduces in those handlers must have offset the simpler HW (I assume that was their goal). The OS people must have shitted some bricks, but then again maybe that is the reason why HP-UX was so "unique." HP sure did have some odd "isms."

I should be fair and balanced like Fox News. It did include a load of things like shadow and scratch registers etc. to give some room to work in - more so than any other architecture until Itanium, but IMHO, the overall design was still pointlessly complicated. Maybe we will see a tell-all "Confessions of a CPU Architect" book some day where they will explain the real reasons why they do these things (they were hungover the day they designed that feature... etc).

Simics is now a commercial product, and supports a whole raft of targets. SPARC is probably the best represented, with emulated SunFire 3800-6800 (US3/4) with multiple processors, and also the Blade 1500. I also seem to remember an emulated target for the T1/Niagra, but don't see the docs around now. Also supported is an EV5 AlphaPC, ARM5, Itanium, various PPC flavors, MIPS Malta, and x86. Although the x86 will run Windows, and the Suns will run Solaris, the other targets only support Linux, and are mostly useful for embedded development.

Yeah, I knew about the commercialised version from Virtutech (and also the cost!) but didn't know they had free student licenses, so I didn't mention it. Though Solaris/SPARC is essentially the same code as Solaris/Intel, so it is as easy to just run it natively, or in an X86 emulator/virtual machine.

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R-ten-K
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Re: Unix Emulation

Unread postby R-ten-K » Tue Nov 04, 2008 4:38 am

If you can access some back issues (as in 80s vintage) of IEEE Computer magazines, you will read some very candid articles which include the design decisions/trade offs behind some of the major architectures. Attending some of the panels at ISCA/MICRO/ASPLOS, ISSCC, or hotchips is always a hoot when interacting with industry people.

From what I have read, It seems that the HP-PA was truly made by committee: it was based on a previous CISC effort, had to support their legacy minis, and someone decided to bolt on the latest "RISC" fad to make it buzzword compliant. But it always seemed like an odd RISC. I think the feature I remember was their odd cache strategy: usually they implemented a single very large cache level. Which from what I was told, was probably because they had some serious issues with register spills. And now that you brought the handler issues, it makes a lot of sense to have a big honking cache when so much overhead is expected when servicing interrupts, exceptions, etc.

I also remember that at some point, the next generation Amigas were supposed to be based around HP-PA? It must have been weird to be motorola in the 80s, everyone leaving you for yet another RISC vendor.
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Re: Unix Emulation

Unread postby hamei » Sat Nov 08, 2008 3:24 am

kramlq wrote:I should be fair and balanced like Fox News.

Ah, the Liberal media !

Thanks, kramlq, laughed out loud at that one :D

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Re: Unix Emulation

Unread postby hamei » Sat Nov 08, 2008 3:26 am

hamei wrote:
kramlq wrote:I should be fair and balanced like Fox News.

Ah, the Liberal media !

Thanks, kramlq, laughed out loud at that one :D


While we've got you two dissecting the shortcomings in processors, how about the Power lineup ? And where does the Itanic really fit in ? Would it have been the processor to end all processors if it hadn't been such a bust ?

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Re: Unix Emulation

Unread postby kramlq » Sat Nov 08, 2008 12:41 pm

R-ten-K wrote: I think the feature I remember was their odd cache strategy: usually they implemented a single very large cache level.... And now that you brought the handler issues, it makes a lot of sense to have a big honking cache when so much overhead is expected when servicing interrupts, exceptions, etc.

Yeah, even today, the last generation PA-RISCs have 32 and 64Mb L2 caches. I'm not sure why they do that.

R-ten-K wrote:
It must have been weird to be motorola in the 80s, everyone leaving you for yet another RISC vendor.

I was at Motorola in the 90's and they were still in the process of moving 68k based UNIX boxes used internally to competitors CPU's (mostly PA-RISC). All the 68k based Macs were being replaced as well, but at least they had a stake in PowerPC, so it wasn't all bad.

hamei wrote:While we've got you two dissecting the shortcomings in processors, how about the Power lineup ? And where does the Itanic really fit in ? Would it have been the processor to end all processors if it hadn't been such a bust ?

I have never really used POWER systems - I've only read some of the papers on POWER and AIX. It is actually a couple of similar architectures in one (to support old POWER 32 & 64 bit, PowerPC-AS, PowerPC 32 & 64 bit). Plus it has great virtualisation support (in combination with firmware), and they have also started to implement hardware assists for commonly needed stuff at OS level. And it achieves decent clock speeds. All in all, a nice chip, and a shame it isn't being used more widely.

Ahh. Itanium
... take many PA-RISC features (already overly complicated from an OS point of view)
... add things like register window concept from SPARC, some of MIPS CP0 features, the PALcode idea from Alpha,
... add a huge number of registers, so that normal context switching strategies are not feasible. Ensure that lazy strategies are needed, and thus complicated stack unwinding is needed when something needs to access the register file of a suspended thread.
... then implement full IA-32 compatibility in hardware (i.e. one of the most complicated and kludged architectures ever).
... then for the ISA, use an explicitly parallel design that puts a massive burden of work on compiler writers (and also those writing assembly for the kernel and libraries).

I was never impressed with it from the start, and wasn't the least bit surprised that what seemed like the underdog (AMD Hammer, now AMD64) took the role expected of the mighty Itanium in the 64-bit world. Its actually funny - I recall around 1999 or so seeing graphs projecting annual shipment of 30 million itanium based systems just a few years later. Its a shame several decent architectures (Alpha, and MIPS to an extent) got killed off for what turned out to be a commercial flop. Admittedly it did do FP well, and scientific sales are probably the only thing that justifies keeping it alive nowadays.

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Re: Unix Emulation

Unread postby R-ten-K » Sun Nov 09, 2008 2:20 pm

Itanic technically it is a dog, however it seems that in hindsight it must have been a marketing tour de force since it did annihilate the competition: AXP, MIPS, and to a lesser extent SPARC/POWER. Which I guess, under Intel's POV, it must have been a worthy investment.

I can't believe the IA64 people decided to implement register windows. When I was in grad school, one of the projects I had to develop an out-of-order scheduler for a machine with register windows (SPARC). And it was a massive pain in the ass... I was impressed when I read that the itanium people had managed to get an out-of-order implementation internally, but I assume it is so complex as to not be worth it.

I liked the concept of predication, but now it is clear that it is a bad idea from a power consumption standpoint.

Power may not be around for long, I think most of Power7 is subsidised by DARPA. Power6 is interesting, in the sense that IBM decided to ditch out of order and go for sheer speed. Still, they do some really strange things to that architecture, like the decimal ALUs (ugh).

If anything, the only architecture I am looking forward to see release soon is ROCK from SUN. It is mighty late, but I am interested in seeing an actual implementation of transactional memory. Although, after playing with nehalem... I hope the sun people get it right.
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Re: Unix Emulation

Unread postby Sacrifist » Tue Nov 11, 2008 7:53 pm

R-ten-K wrote:...
I also remember that at some point, the next generation Amigas were supposed to be based around HP-PA? It must have been weird to be motorola in the 80s, everyone leaving you for yet another RISC vendor.


It was called Hombre, pardner!
http://en.wikipedia.org/wiki/Hombre_chipset

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Re: Unix Emulation

Unread postby Alver » Wed Nov 12, 2008 4:36 am

kramlq wrote:Ahh. Itanium
... take many PA-RISC features (already overly complicated from an OS point of view)
... add things like register window concept from SPARC, some of MIPS CP0 features, the PALcode idea from Alpha,
... add a huge number of registers, so that normal context switching strategies are not feasible. Ensure that lazy strategies are needed, and thus complicated stack unwinding is needed when something needs to access the register file of a suspended thread.
... then implement full IA-32 compatibility in hardware (i.e. one of the most complicated and kludged architectures ever).
... then for the ISA, use an explicitly parallel design that puts a massive burden of work on compiler writers (and also those writing assembly for the kernel and libraries).


Actually, that feature was dropped completely, and is now handled entirely in the IA32 Execution Layer, which is software. And, from experience, it is never, ever used.

Itanium2 is not a bad chip. It's definitely not the best - I'm sure some people here can debate for weeks over this title :D - but it's really not a bad chip. Combined with the chipsets HP provides (ZX2, ZX2000) it has an interesting amount of total I/O and memory bandwidth. It never had that funky take-cover-im-a-RISC feeling you get from MIPS, Sparc, POWER, HPPA, ... though.
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Re: Unix Emulation

Unread postby kramlq » Wed Nov 12, 2008 11:36 am

Alver wrote:
kramlq wrote:Ahh. Itanium
... take many PA-RISC features (already overly complicated from an OS point of view)
... add things like register window concept from SPARC, some of MIPS CP0 features, the PALcode idea from Alpha,
... add a huge number of registers, so that normal context switching strategies are not feasible. Ensure that lazy strategies are needed, and thus complicated stack unwinding is needed when something needs to access the register file of a suspended thread.
... then implement full IA-32 compatibility in hardware (i.e. one of the most complicated and kludged architectures ever).
... then for the ISA, use an explicitly parallel design that puts a massive burden of work on compiler writers (and also those writing assembly for the kernel and libraries).


Actually, that feature was dropped completely, and is now handled entirely in the IA32 Execution Layer, which is software. And, from experience, it is never, ever used.

I know. If you read it again, you'll see I was giving my take on the design process for the Itanium architecture. The process of designing Itanium (or IA64 as it was called back then) happened a long time before Itanium2 chips (i.e. implementation) arrived, and back then, they decided to have full IA-32 compatibility on chip.

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Re: Unix Emulation

Unread postby porter » Wed Nov 12, 2008 12:26 pm

kramlq wrote:... they decided to have full IA-32 compatibility on chip.


Presumably the folks at Intel believe you can never have too much backward compatibility.
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