rooprob wrote:
On the subject of the O2 display. I found that whilst 1600x1200 and 1680x1050 do render, something isn't quite right.
Thanks for the feedback. I don't have monitors in a number of the resolutions offered, nor an O2 to test with.
I'm not at all surprised that neither mode would work with your HP 2475w. I used the the version of CVT you so kindly ported to IRIX to generate the modelines I used, so we most likely built identical formats. I'll take them down if I don't soon hear they'll work different model monitors (other than the L2475w).
In any case, thank you for porting CVT, and
I've previously recommended your modelines script as an excellent VFC resource.
It's possible that the analog port on the O2 may be running into a hardware limitation with display resolutions wider than 1600 active pixels per line. I'm sure rooprob has seen it, but for those who haven't, VFC errors out if there are more than 2160 TotalPixelsPerLine in an O2 VFC source file. The CVT reduced blanking 1680x1050 modeline was enough to reduce the TPPL to less than 2160 limit, but may have introduced other timing issues. rooprob, If you haven't already tried you might see if changing the accumulation buffer setting in xsetmon to 'software only' (16 bits-per-component) helps with OpenGL visuals.
On the slim chance that you haven't already seen (or tried) it, SGIFanLongTime posted a 1920x1080_59.95 VFC source file that apparently worked with his O2 (he didn't mention what monitor it was intended for):
viewtopic.php?f=3&t=13591&start=30#p7276037If you can get relatively close to a usable display, the position of the viewable portion of the display can be tweaked by manually adjusting the values in the modeline. There's a brief description of the process about halfway down in this post:
viewtopic.php?f=3&t=16725716#p7343498EDIT: @rooprob -
In this post schleusel mentioned a workaround for getting 1680x1050 working with an analog-friendly pixel clock (which is probably more suitable suitable for the analog O2 CRM graphics than a intended-for-DVI reduced blanking modeline). The vfo files schleusel created and hosted on line aren't there any more, but I followed his mention of reducing the TPPL to 2160 by reducing the HBP by 80 pixels. The resulting format source compiled without error, I've added it to the list at the beginning of the thread. If you try it let me know if it works.
Here's the VFC analysis:
Code:
O2_1680x1050_60-analog.vfo:
Total lines per frame: 1089
Total pixels per line: 2160
Active lines per frame: 1050
Active pixels per line: 1680
Frames per second: 60
Fields per frame: 1
Swaps per frame: 1
Pixel clock: 141.134 MHz, period = 7.08544 nsec
Hardware pixel rounding: every 1 pixels
Line analysis:
Length: 2160 Pixels, 1 Lines, 15.3046 usec; (line 0)
Frequency: 65.34 KHz, period = 15.3046 usec
Horizontal Sync: 176 Pixels, 1.24704 usec; (line 36)
Horizontal Back Porch: 200 Pixels, 1.41709 usec; (line 36)
Horizontal Active: 1680 Pixels, 11.9035 usec; (line 36)
Horizontal Front Porch: 104 Pixels, 736.886 nsec; (line 36)
Field Information:
Field Duration: 2.35224e+06 Pixels, 1089 Lines, 16.6667 msec; (line 0)
Vertical Sync: 15120 Pixels, 7 Lines, 107.132 usec; (line 0)
Vertical Sync Pulse: 15296 Pixels, 7.08148 Lines, 108.379 usec; (line 0)
Vertical Back Porch: 62640 Pixels, 29 Lines, 443.832 usec; (line 7)
Vertical Active: 2.268e+06 Pixels, 1050 Lines, 16.0698 msec; (line 36)
Vertical Front Porch: 6480 Pixels, 3 Lines, 45.9137 usec; (line 1086)
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