so we have:
4 to 5 GHz
13 stage pipeline
large on die L2 cache, not shared
on die L3 memory controller
more than 36MB L3cache
maybe L4 cache
A Power-6 workstation would be fun, indeed.
quad Power6, quad 1GB Nvidia Quadro, 256GB FBdimm, Infiniband, SAS storage, Linux or AIX OS.
Greetings from Germany
It is confirmed that POWER6 has:
- Single-instruction-latency FXU
- Higher dispatch bandwith of 7 for SMT compared to Power5's 5.
- 64kb L1D cache (up from 32kb)
- 4MB private L2 cache per core (up from 1.9MB shared)
- Dual memory controllers (instead of 1).
- Pipeline depth of 13 (shorter than Power5's 15)
- Dual thread SMT, with the second thread providing ~40% extra performance for integer and 55% for OLTP benchmarks. (POWER5 was ~20-35%)
- IBM seems to be using different channel length transistors for different frequency points.
- Rumored: No more grouping of instructions
http://www.realworldtech.com/forums/ind ... &roomid=11
Here is IBM's Presentation at FPF:
http://www2.hursley.ibm.com/decimal/IBM ... Credie.pdf
And an abstract from next week's ISSCC:
"The POWER6TM microprocessor combines ultra-high frequency operation, aggressive power reduction, a highly scalable memory subsystem, and mainframe-like reliability, availability, and serviceability. The 341mm2 700M transistor dual-core microprocessor is fabricated in a 65nm SOI process with 10 levels of low-k copper interconnect. It operates at clock frequencies over 5GHz in high-performance applications, and consumes under 100W in power-sensitive applications."
We also know that Power6 will be used in Blade servers as well:
We will know more next week when IBM makes their presentation.