ROSS CPU and PROM question (SS20)

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tesla
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ROSS CPU and PROM question (SS20)

Unread postby tesla » Fri Apr 18, 2008 7:27 am

My dual 100MHz ROSS-module just arrived today and since I have read that I need PROM-version 2.25 to use this module I was quite surprised when it booted right up and loaded Linux without a hitch. The PROM clearly states ver 2.15.

Is there some downside to this in functionality although it works, or is the information I've read incorrect? The machine feels quite a bit faster than before and Linux(SuSE) identifies the CPU-module correct so I'm a little bit confused at the moment.

Oh, and I read somwhere that you can't mix CPU-boards of different speed. Does that apply to both superSPARC and hyperSPARC modules or is that some inherent limitation in the Prom?

/Matt
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SAQ
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Re: ROSS CPU and PROM question (SS20)

Unread postby SAQ » Fri Apr 18, 2008 6:17 pm

For Sun4m architecture machines, you need to have the same type of CPU (SPARC (SM100, the old dual 40MHz SPARCv7 chips), SuperSPARC, or HyperSPARC), the same MBus speed, and the same MXCC revision. You also can't mix modules with and withoute ECache. Other than that, it works fine.

On the Ultra boxes they need to be matched speedwise. Sliding backwards :( .

I know POWER series SGIs can use mixed speed boards, and the ccNUMA boxes can have different node speeds. How about the Everests? Any other boxes that can use mixed-speed CPUs (in a closely-coupled setup, no VMSclusters or Beowulfs, and I'm not sure if this would even include the SNx-IRISes).
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tesla
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Re: ROSS CPU and PROM question (SS20)

Unread postby tesla » Sat Apr 19, 2008 5:40 am

For Sun4m architecture machines, you need to have the same type of CPU (SPARC (SM100, the old dual 40MHz SPARCv7 chips), SuperSPARC, or HyperSPARC), the same MBus speed, and the same MXCC revision. You also can't mix modules with and withoute ECache. Other than that, it works fine.

On the Ultra boxes they need to be matched speedwise. Sliding backwards :( .


Ok, so it could be possible to get let's say a dual ROSS 125MHz module or some other hyperSPARC module and get it working? Would be nice since 2x100's aren't the most available. I also saw that the HS14 isn't supported by some *NIX'es.

I know POWER series SGIs can use mixed speed boards, and the ccNUMA boxes can have different node speeds. How about the Everests? Any other boxes that can use mixed-speed CPUs (in a closely-coupled setup, no VMSclusters or Beowulfs, and I'm not sure if this would even include the SNx-IRISes).


Well, how about PC's. In many dual mainboards you can have CPU's of different speeds. :D Oh, well, let's not mix the PC in here.

/Matt
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Re: ROSS CPU and PROM question (SS20)

Unread postby SupremeCmdr » Sat Apr 19, 2008 11:29 pm

tesla wrote:Oh, and I read somwhere that you can't mix CPU-boards of different speed. Does that apply to both superSPARC and hyperSPARC modules or is that some inherent limitation in the Prom?

/Matt


From my research when I had a SS20, you couldn't mix modules that were cache-less but certain other modules were safe to mix. I never managed to test this out so it's all here-say.

A quick lookup on SunStuff should give you the part numbers for cache-less modules
This MBUS Guide site was in my bookmarks from a while ago.

Have a troll through the NetBSD mailing list for SPARC, they seem to have problems with cacheless chips and some people are running mixed speed SuperSPARC and HyperSPARC modules. YMMV
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