Code: Select all
Hardware Power ON
@(#)OBP 4.17.1 2005/04/11 14:31
Executing Power On SelfTest
@ig =0x0000003e.000ST 2.0.1 05:13 PM on 08/23/01
CPU UPA conf37:36] =0x00000003
ELIM[35:33] =0x00000007
PC00
CLK_MODE[000000
module_type1:17] =0x00000000
PCAP[16:0] =0x00Processor Module Identification
UltraSPARC-IIe+ (P33000507
7/03 1968
Init P [hour:min:sec] 06:04:49 [month/date year] 0in:sec] 06:04:49 [month/date year] 07/03 1968
NVtamp [hour:mtch Data Test
Time Stamp [hour:min:sec] 06:04:49 [month/date year] 07/03 1968
DMMU TLB Tags
DMMU TLB Tag Access Test
Time Stamp [hour:min:sec] 06:04:49 ss Test
te year] 07/03 1968
DMMU TLB RAM
DMMU TLB RAM Access Test
Time Stamp [hour:miProbe Ecache
ecache_size: RAM r] 07/03 1968
Probe Ecache
0000 bytes
Ecache Size = 0x00080000 bytes = 512 KBytes
Time Sasure CPU Clock
Initializing Sonth/date year] 07/03 1968
Measure CPU Clock
Initializing Southbridge
ar] 07/03 1968
Measure CPU Clock
Initializing Southbridge
Measurime Stamp [hour:min:sec] 06:04:57ominal CPU speed is 649 MHz
T
All CPU Basic Tests
V9 Instruction Test
CPU Tick and Tic
Compare Reg Test
sts
V9 Instruction Test
CPU Tick and Tick Compare Reg Test
CPU Soft Trap Test
CPU Softintte year] 07/03 1968
e Stamp [hour:min:sec] 06:04:59 [month/dat Reg Test
All Basic MMU Tests
DMMU Primary Contex
Reg Test
DMMU Secondary Context Reg Test
DMMU TSB Reg Test
DMMU Tag Access Reg Test
DMMU VA Watchpoint Reg Test
DMMU PA Watchpoint Reg Test
IMMU TSB Reg Test
IMMU Tag Access Reg Test
All Basihour:min:sec] 06:04:59 [month/date year] 07/03 1968
All Basic Cache Tests
Dcache RAM Test
Dcache Tag Test
Icache RAM Test
Icache Tag Test
Icache Next Test
Icache Predecode Test
MCU Control & in:sec] 06:05:13 [month/date year] 07/03 1968
isters
DIMM0 freq byte = 0x64
DIMM3 freq byte = 0x64and MC regMhz, dimm_freq=
set_mc0(): cpu_freq= 649o= 649
set_mc0(0): mdp_mcu_clk_ratio = 0x000000o_sdram_clk_ratio= 649
set_mc0(0): mdp_mcu_clk_ratio = 0x00000000.80000000
atio= 649
set_mc0(0): mdp_mcu_clk_ratio = 0x00000000.80000000
ref_interval = 79 = 0x4f, DIMM 0: 512 MBytes = 0x200000Bytes = 0x20000000 bytes
DIMM 3x20000000 bytes
DIMM 2: 512 M
Found 1 DIMMs in system
Found 2 DIMMs in system
Found 3 D 0
Bank 0: 2048 MBytes
DIMM0 system
Found 4 DIMMs in bank8 dev x 8 device
DIMM2 is a 32M x 8 device
DIMM3 is a 32M x m = 18 chips
dimm_spd[2].chips_num =chips
dimm_spdMC3 = 0x00000000.00600bff upa_config is 0x0000003
CP:sec] 06:05:15 [month/date year] 07/03 1968
Ecache Tests
Displacement Flush Ecache
e year] 07/03 1968
Ecache Tests
Displacement Flush Ecache
Ecache RAM Addr Test
ecache_ram_addr_line():
wriaddr 0x00000000.00000008
writiing data 0xffffffff.fffffff7 at ddr 0x00000000.00000010
writing data 0xffffffff.ffffffdf at adr 0x00000000.00000040
writing ddata 0xffffffff.ffffffbf at add 0x00000000.00000080
writing data 0xffffffff.fffffeff at addr x00000000.00000200
writing dataa 0xffffffff.fffffdff at addr 0000000.00001000
writing data 0xxffffffff.ffffefff at addr 0x0000000.00002000
writing data 0xffffffff.ffffbfff at addr 0x0000000.00008000
writing data 0xfffffffff.ffff7fff at addr 0x0000000.00010000
writing data 0xffffffff.fffdffff at addr 0x0000000000040000
Ecache Tag Addr Test
ff.fffbffff at addr 0x00000000.00040000
Ecache Tag Addr Test
ff.fffbffff at addr 0x00000000.00040000
Ecache Tag Addr Test
ff.fffbffff at addr 0x00000000.00040000
Ecache Tag Addr Test
Ecache Size = 0x00080000 bytes = 512 KBytes
Ecache RAM Test
Ecache Tag Test
Time Stamp Init
Malloc Post Memory
postdate year] 07/03 1968
Memory000000.00000000
Memory Addr Check w/o Ecache
Load Post 0x00mory
Run POST from MEM
.r Check w/o Ecache
Load Post In Memory
Run POST from MEM
.........
Time Stamp [hour:min:seMU
Update Master Stack/Frame Pointers
8
All FPU Basic Tests
FPU Regs Test
h/date year] 07/03 196FPU
All FPU Basic Tests
FPU Regs Test
FPU Move Regs Test
tamp [hour:min:sec] 06:05:43 [monthTest
FPU Trap Test
Time S Teasic IOMMU Tests
PIO Decoder and BCT Test
PCI Byte Enables IOMMU CAM Address Test
IOMMU TLBs IOMMU RAM Addr Test
CPU'ush Test
PBMA PCI Config Space RLB Compare Test
IOMMU TLB Fl[Reg Test
PBMA Diag Reg Test
CPU's IO Regs Test
Time Stamp anced CPU Tests
DMMU Hit/Miss Tate year] 07/03 1968
All Adv Little Endian Test
IU ASI Access Test
FHit/Miss Test
DMMUe data 0x5555.55555555 to addr 0x00000000.000.00800008
wrote data 0x5555555555555 to addr 0x00000000.00800018
wrote data 0x55555555.555555o addr 0x00000000.00800028
wroterote data 0x55555555.55555555 tdr 0x00000000.00800030
wrote data 0x55555555.55555555 to addr 000000.00800040
wrote data 0xaaaaaaaaaaaa.aaaaaaaa to addr 0x00088
wrote data 0xaaaaaaaa.aaaaaaaaaaaa to addr 0x00000000.0080005rote data 0xaaaaaaaa.aaaaaaaa to addr 0x00000000.00800068
wrotea 0xaaaaaaaa.aaaaaaaa to addr 0xr 0x00000000.00800070
wrote dat55555555.55555555 to addr 0x00000000.00800000
wrote data 0x5555.55555555 to addr 0x00000000.008000800008
wrote data 0x555555555addr 0x00000000.00800028
wrote ote data 0x55555555.55555555 to 0x00000000.00800030
wrote data 0x55555555.55555555 to addr 0x0000.00800040
wrote data 0xaaaaaaaaaaaa.aaaaaaaa to addr 0x0000000800048
wrote data 0xaaaaaaaa.aaaaaaaa to addr 0x00000000.0080
wrote data 0xaaaaaaaa.aaaaaaaaaaaa to addr 0x00000000.00800058d0xaaaaaaaa.aaaaaaaa to addr 0x000x00000000.00800070
wrote data 555555.55555555 to addr 0x00000000.00800000
wrote data 0x5555555555555 to addr 0x00000000.008000800008
wrote data 0x55555555.5555 to addr 0x00000000.00800018
wrote data 0x55555555.55555555 ddr 0x00000000.00800028
wrote dte data 0x55555555.55555555 to a00.00800040
wrote data 0xaaaaaaaaaaaa.aaaaaaaa to addr 0x0000000800048
wrote data 0xaaaaaaaa.aaaaaaaa to addr 0x00000000.008000wrote data 0xaaaaaaaa.aaaaaaaa taa to addr 0x00000000.00800058
e data 0xaaaaaaaa.aaaaaaaa to addr 0x00000000.00800068
wrote daxaaaaaaaa.aaaaaaaa to addr 0x000x00000000.00800070
wrote data 0555555 to addr 0x00000000.008000800008
wrote data 0x55555555.5555 to addr 0x00000000.00800018
wrote data 0x55555555.55555555 tor 0x00000000.00800028
wrote dae data 0x55555555.55555555 to add00000000.00800030
wrote data 0x55555555.55555555 to addr 0x0000.00800040
wrote data 0xaaaaaaaaaaaa.aaaaaaaa to addr 0x0000000000048
wrote data 0xaaaaaaaa.aaaaaaaa to addr 0x00000000.0080005rote data 0xaaaaaaaa.aaaaaaaa tor 0x00000000.00800068
wrote dat data 0xaaaaaaaa.aaaaaaaa to add00000000.00800070
wrote data 0xaaaaaaaa.aaaaaaaa to addr 0x0000.00800000
wrote data 0x555555555555.55555555 to addr 0x0000000000008
wrote data 0x55555555.55555555 to addr 0x00000000.0080001rote data 0x55555555.55555555 to to addr 0x00000000.00800018
wa5555555.55555555 to addr 0x000000000000.00800030
wrote data 0x5aaa.aaaaaaaa to addr 0x00000000.00800040
wrote data 0xaaaaaaaa.aaaa to addr 0x00000000.008000500048
wrote data 0xaaaaaaaa.aaaa to addr 0x00000000.00800058
wrote data 0xaaaaaaaa.aaaaaaaa to 0x00000000.00800068
wrote datadata 0xaaaaaaaa.aaaaaaaa to addr00800000
wrote data 0x55555555.555.55555555 to addr 0x00000000.0008
wrote data 0x55555555.55555555 to addr 0x00000000.00800010
te data 0x55555555.55555555 to ato addr 0x00000000.00800018
wroata 0x55555555.55555555 to addr 0x00000000.00800028
wrote data 555555.55555555 to addr 0x000000000000.00800030
wrote data 0x55aaa to addr 0x00000000.00800050
048
wrote data 0xaaaaaaaa.aaaaaao addr 0x00000000.00800058
wrote data 0xaaaaaaaa.aaaaaaaa to adx00000000.00800068
wrote data 0ta 0xaaaaaaaa.aaaaaaaa to addr 000000.00800070
wrote data 0xaaaaaaaa.aaaaaaaa to addr 0x0000000800000
wrote data 0x55555555.555.55555555 to addr 0x00000000.00w data 0x55555555.55555555 to ado addr 0x00000000.00800018
wrotea 0x55555555.55555555 to addr 0x00000000.00800028
wrote data 0x5555.55555555 to addr 0x000000000000.00800030
wrote data 0x5555.aaaaaaaa to addr 0x00000000.00800040
wrote data 0xaaaaaaaa.aaaa to addr 0x00000000.00800050
w8
wrote data 0xaaaaaaaa.aaaaaaa addr 0x00000000.00800058
wrote data 0xaaaaaaaa.aaaaaaaa to add00000000.00800068
wrote data 0xaaaa.aaaaaaaa to addr 0x000000000000.00800070
wrote data 0xaaaa.55555555 to addr 0x00000000.00800000
wrote data 0x55555555.5555 to addr 0x00000000.00800010
w8
wrote data 0x55555555.5555555 addr 0x00000000.00800018
wrote data 0x55555555.55555555 to add00000000.00800028
wrote data 0x5 0x55555555.55555555 to addr 0x.0040
wrote data 0xaaaaaaaa.aaaaaaaaaaaa to addr 0x00000000.0080
wrote data 0xaaaaaaaa.aaaaaaaa to addr 0x00000000.00800050
wrdata 0xaaaaaaaa.aaaaaaaa to addraddr 0x00000000.00800058
wrote 0xaaaaaaaa.aaaaaaaa to addr 0x00000000.00800068
wrote data 0xaaaa.aaaaaaaa to addr 0x00000000.000.00800070
wrote data 0xaaaaa5to addr 0x00000000.00800010
wrote data 0x55555555.55555555 ddr 0x00000000.00800018
wrote data 0x55555555.55555555 to addr 000000.00800028
wrote data 0x550x55555555.55555555 to addr 0x0000.00800030
wrote data 0x55555555.55555555 to addr 0x00000000.0040
wrote data 0xaaaaaaaa.aaaaaaaaaaaa to addr 0x00000000.00800tta 0xaaaaaaaa.aaaaaaaa to addraddr 0x00000000.00800058
wrote daxaaaaaaaa.aaaaaaaa to addr 0x00000000.00800068
wrote data 0xaaaa.aaaaaaaa to addr 0x00000000.000.00800070
wrote data 0xaaaaaaa555555 to addr 0x00000000.00800000
wrote data 0x55555555.555555o addr 0x00000000.00800010
wrote data 0x55555555.55555555 tdr 0x00000000.00800018
wrote data 0x55555555.55555555 to addr d00000.00800028
wrote data 0x5555.55555555 to addr 0x00000000.000.00800030
wrote data 0x555555aaaaaaa to addr 0x00000000.00800040
wrote data 0xaaaaaaaa.aaaaato addr 0x00000000.00800050
wroterote data 0xaaaaaaaa.aaaaaaaa ddr 0x00000000.00800058
wrote data 0xaaaaaaaa.aaaaaaaa to addr 000000.00800068
wrote data 0xaaaxaaaaaaaa.aaaaaaaa to addr 0x00000
wrote data 0x55555555.555555555555 to addr 0x00000000.008000wrote data 0x55555555.55555555 to addr 0x00000000.00800010
wrotta 0x55555555.55555555 to addr 0dr 0x00000000.00800018
wrote dax55555555.55555555 to addr 0x00000000.00800028
wrote data 0x5555.55555555 to addr 0x00000000.008.00800030
wrote data 0x5555555a addr 0x00000000.00800050
wroterote data 0xaaaaaaaa.aaaaaaaa tor 0x00000000.00800058
wrote data 0xaaaaaaaa.aaaaaaaa to addr 0x0000.00800068
wrote data 0xaaaaaaaaaaaa.aaaaaaaa to addr 0x0000.00800070
wrote data 0xaaaaaaaa.aaaaaaaa to addr 0x00000000.0080
wrote data 0x55555555.555555555555 to addr 0x00000000.0080000 0x55555555.55555555 to addr 0x0 0x00000000.00800018
wrote data5555555.55555555 to addr 0x00000000.00800028
wrote data 0x5555555555555 to addr 0x00000000.008000800030
wrote data 0x55555555.aaaa to addr 0x00000000.00800040
wrote data 0xaaaaaaaa.aaaaaaaaaddr 0x00000000.00800050
wrote ote data 0xaaaaaaaa.aaaaaaaa to 000.00800068
wrote data 0xaaaaaaaaaaaa.aaaaaaaa to addr 0x0000000800070
wrote data 0xaaaaaaaa.aaaaaaaa aaa to addr 0x00000000.00800040
te data 0xaaaaaaaa.aaaaaaaa to addr 0x00000000.00800050
wrote d0xaaaaaaaa.aaaaaaaa to addr 0x000x00000000.00800058
wrote data aaaaaaa to addr 0x00000000.008000800070
wrote data 0xaaaaaaaa.aaaa to addr 0x00000000.00800040
wrote data 0xaaaaaaaa.aaaaaaaa tdr 0x00000000.00800050
wrote dte data 0xaaaaaaaa.aaaaaaaa to adx00000000.00800058
wrote data 0xaaaaaaaa.aaaaaaaa to addr 0x0000.00800068
wrote data 0xaaaaaaaaaaaa.aaaaaaaa to addr 0x0000000800070
wrote data 0xaaaaaaaa.aaaaaaaa to addr 0x00000000.008000wrote data 0x55555555.55555555 ddr 0x00000000.00800010
wrote dae data 0x55555555.55555555 to a0x00000000.00800018
wrote data 0x55555555.55555555 to addr 0x0000.00800028
wrote data 0x555555555555.55555555 to addr 0x0000000800030
wrote data 0xaaaaaaaa.aaaaaaaa toa to addr 0x00000000.00800040
axaaaaaaaa.aaaaaaaa to addr 0x000000000000.00800058
wrote data 0aaaaa.aaaaaaaa to addr 0x00000000.00800068
wrote data 0xaaaaaaaaaaaaa to addr 0x00000000.008000700070
wrote data 0xaaaaaaaa.aao5 to addr 0x00000000.00800000
wrote data 0x55555555.55555555 tdr 0x00000000.00800010
wrote dat data 0x55555555.55555555 to ad0000000028
wrote data 0x55555555.555.55555555 to addr 0x00000000.0080
wrote data 0x55555555.55555555 to addr 0x00000000.00800038
w data 0xaaaaaaaa.aaaaaaaa to addraddr 0x00000000.00800040
wrotea 0xaaaaaaaa.aaaaaaaa to addr 0x00000000.00800050
wrote data 0xaaaa.aaaaaaaa to addr 0x00000000.000.00800058
wrote data 0xaaaaa to addr 0x00000000.00800078
wr
wrote data 0xaaaaaaaa.aaaaaaaaaddr 0x00000000.00800000
wrote data 0x55555555.55555555 to addr0000000.00800010
wrote data 0x5 0x55555555.55555555 to addr 0x0000.00800018
wrote data 0x55555555.55555555 to addr 0x00000000.0028
wrote data 0x55555555.555555555555 to addr 0x00000000.0080oata 0xaaaaaaaa.aaaaaaaa to addr ddr 0x00000000.00800040
wrote d0xaaaaaaaa.aaaaaaaa to addr 0x00000000.00800050
wrote data 0xaaaa.aaaaaaaa to addr 0x00000000.000.00800058
wrote data 0xaaaaaaaaaaaaa to addr 0x00000000.00800068
wrote data 0xaaaaaaaa.aaaaato addr 0x00000000.00800078
wrote data 0xaaaaaaaa.aaaaaaaa 000000.00800010
wrote data 0x555x55555555.55555555 to addr 0x0000.00800018
wrote data 0x55555555.55555555 to addr 0x00000000.0028
wrote data 0x55555555.555555555555 to addr 0x00000000.008000wrote data 0x55555555.55555555 to addr 0x00000000.00800038
wrotta 0xaaaaaaaa.aaaaaaaa to addr 0dr 0x00000000.00800040
wrote daa.aaaaaaaa to addr 0x00000000.000.00800058
wrote data 0xaaaaaaaaaaaaa to addr 0x00000000.00800068
wrote data 0xaaaaaaaa.aaaaaaa addr 0x00000000.00800078
Ecacrote data 0xaaaaaaaa.aaaaaaaa to addr 0x00000000.00800078
Ecache Thrash Test
aaaa.aaaaaaaa to addr 0x00000000.00800078
Ecache Thrash Test
Time Stamp [hour:min:sec] 06:06:02 [month/date year] 0p Test
CPU Addr Align Trap Testing Tests
CPU Data Access Tra DMMU Write Protected Page Test
Time Stamp [hour:min:sec] 06:06ice PCI Config Registers Test
A
Audio Tests
Map Audio Devv545110b9) Test
Init Audio Device IO Registers Test
Audio De[month/date year] 07/03 1968
MStamp [hour:min:sec] 06:06:02 z ends@addr+size=0x00000000.20000starts@addr=0x00000000.00800000,00016
CPU MODULE upa_config is 0x0000003a.00000000
Init with 0x00000000.00000000:
...................................t with...............................................................................................1
Start Adx i=00000000.20000000
Info : 512MB at Divmem_bank_clr(): starts@addr=0x00000000.40000000, ends2 MBytes
LE upa_config is 0x000PSTATE reg = 0x00000000.00000016
CPU MODU00000:
......................000000
Init with 0x00000000.000.................................................................................................................
last index i=00000000.6000000000 Size: 512 MBytes
vmem_bank
Start Addr: 0x00000000.800000000000, ends@addr+size=0x00000000.a0000000
Init with 0x00000000.00000000:
onfig is 0x0000003a.00000000
...............000000.00000000:
........................................................................................................................................3
Start Addr: 0x000000.a0000000
Info : 512MB at Dimm m_bank_clr(): starts@addr=0x00000000.c0000000, ends@addr+es
vmeupa_config is 0x0000003a. reg = 0x00000000.00000016
CPU MODULE 00:
.........................000
Init with 0x00000000.000000..............................................................................................................
last index i=00000000.e0000000
: 512MB at Dimm Slot 0
Start Ad
mem_diagnl_tst(1):
Info 504 MBytes
Write 0xffffffff.ffffffff: ....0000.00800000 Size: 504 MBytes
Write 0xffffffff.ffffffff: ..............................................................................................................
Read: ...................................................................................................................................
Write 0xaaaaaaaa.aaaaaaaa: ..............................................................................................................
Read: ...................................................................................................................................
Write 0x55555555.55555555: ..............................................................................................................
Read: ...................................................................................................................................
Write 0x00000000.00000000: ..............................................................................................................
Read: ...................................................................................................................................
mem_diagnl_tst(1):
Info : 512MBytes
Write 0xffffffff.ffffffff:x00000000.40000000 Size: 512 MBytes
Write 0xffffffff.ffffffff: ..............................................................................................................
Read: ...................................................................................................................................
Write 0xaaaaaaaa.aaaaaaaa: ..............................................................................................................
Read: ...................................................................................................................................
Write 0x55555555.55555555: ..............................................................................................................
Read: ...................................................................................................................................
Write 0x00000000.00000000: ..............................................................................................................
Read: ...................................................................................................................................
mem_diagnl_tst(1):
Info : 512MBytes
Write 0xffffffff.ffffffff: 00000000.80000000 Size: 512 MBytes
Write 0xffffffff.ffffffff: ..............................................................................................................
Read: ...................................................................................................................................
Write 0xaaaaaaaa.aaaaaaaa: ..............................................................................................................
Read: ...................................................................................................................................
Write 0x55555555.55555555: ..............................................................................................................
Read: ...................................................................................................................................
Write 0x00000000.00000000: ..............................................................................................................
Read: ...................................................................................................................................
mem_diagnl_tst(1):
Info : 512MB at
Write 0xffffffff.ffffffff: 00000000.c0000000 Size: 512 MBytes
Write 0xffffffff.ffffffff: ..............................................................................................................
Read: ...................................................................................................................................
Write 0xaaaaaaaa.aaaaaaaa: ..............................................................................................................
Read: ...................................................................................................................................
Write 0x55555555.55555555: ..............................................................................................................
Read: ...................................................................................................................................
Write 0x00000000.00000000: ..............................................................................................................
Read: ...................................................................................................................................
Block Memory Addr Test
Info : 512MB ats
Info : 512MB at Dimm Slot 1
00000.00800000 Size: 504 MByte000 Size: 512 MBytes
Info : 512MB at Dimm Slot 2
Start Adm Slot 3
Start Addr: 0x00000002 MBytes
Info : 512MB at Dim lock Memory Check Test
memory_blk_check_tst(): bank = 0, *sz =at Dimm Slot 0
Start Addr: 0x0aaaaa.aaaaaaaa
Info : 512MB xize=0x00000000.1f800000 ecc=0
(1): addr=0x00000000.00800000 s
CPU MODULE upa_config is 0x0000003a.00000000
ecc=FALSE
Write 0x33333333.33333333 ....................................
Wri......................................................................................................................................
Read ....................................................................................................................................
Write 0x55555555.55555555 ...............................................................................................................
Read ....................................................................................................................................
Write 0xcccccccc.cccccccc ...............................................................................................................
Read ....................................................................................................................................
Write 0xaaaaaaaa.aaaaaaaa ...............................................................................................................
Read ...................................................................................................................................1
Start Addr: 0x00000000.00000.20000000, *pa = 0x00000000.40000000
mem_c(1): *sz = 0x000eg = 0x00000000000000 size=0x00000000.20000000 ecc=0
PSTATE r000000
ecc=FALSE
Write 0x33333333.33333333 .is 0x0000003a.00...............................333333.33333333 ...............................................
Read ....................................................................................................................................
Write 0x55555555.55555555 ...............................................................................................................
Read ....................................................................................................................................
Write 0xcccccccc.cccccccc ...............................................................................................................
Read ....................................................................................................................................
Write 0xaaaaaaaa.aaaaaaaa ...............................................................................................................
Read ....................................................................................................................................
Info : 512MB at Dimm Slot 2
Start Ad2): *sz = 0x00000000.20000000, *p2 MBytes
memory_blk_check_tst(eck_blk(1): addr=0x00000000.80000000 size=0x00000000.20000000 s 0x0000003a.00000000
ecc=FALS000016
CPU MODULE upa_config i...............................LSE
Write 0x33333333.33333333 ...............................................................................................................
Read ....................................................................................................................................
Write 0x55555555.55555555 ...............................................................................................................
Read ....................................................................................................................................
Write 0xcccccccc.cccccccc ...............................................................................................................
Read ....................................................................................................................................
Write 0xaaaaaaaa.aaaaaaaa ...............................................................................................................
Read ....................................................................................................................................
Info : 512MB aes
memory_blk_check_tst(3): *sz0000000.c0000000 Size: 512 MByt00000000.c0000000
mem_check_blk(1): addr=0x00000000.c0000000 s
CPU MODULE upa_config is 0x0000STATE reg = 0x00000000.00000016te 0x33333333.33333333 .....................00
ecc=FALSE
Wri......................................................................................................................................
Read ....................................................................................................................................
Write 0x55555555.55555555 ...............................................................................................................
Read ....................................................................................................................................
Write 0xcccccccc.cccccccc ...............................................................................................................
Read ....................................................................................................................................
Write 0xaaaaaaaa.aaaaaaaa ...............................................................................................................
Read ....................................................................................................................................
dr: 0x00000000.00800000 Size: 5012MB at Dimm Slot 0
Start Ad00000.00800000 size=0x1f800000
mem_addr(1): addr = 0x00000000.CC error when testing address lin000
ecc = TRUE
mem_addr(2)
Er0000010 at addr 0x00000000.00800000
ECC error when testing add00.00800010
ECC error when testi00000.00000010 at addr 0x000000eaddr 0x00000000.00800030
ECC errpattern 0x00000000.00000010 at th addr pattern 0x00000000.00000010 at addr 0x00000000.00800040
0.00000010 at addr 0x00000000.008in0
ECC error when testing address line with addr pattern 0x00000 address line with addr pattern 008000a0
ECC error when testing000000.008000b0
ECC error when testing address line with addr pr when testing address line with r 0x00000000.008000c0
ECC erron0e0
ECC error when testing addr0000010 at addr 0x00000000.0080000000.00000010 at addr 0x00000000.008000f0
mem_addr(2)
ECC err00 at addr 0x00000000.00800000
ECC dr pattern 0x00000000.0000010010with addr pattern 0x00000000.00000100 at addr 0x00000000.0080000000.00000100 at addr 0x00000000.0 li0
ECC error when testing address line with addr pattern 0x00ing address line with addr patter0.00800700
ECC error when testrror when testing address line witddr 0x00000000.00800900
ECC er100 at addr 0x00000000.00800a00
ECC error when testing address 800b00
ECC error when testing a0.00000100 at addr 0x00000000.00s0000000.00000100 at addr 0x00000000.00800c00
ECC error when te 0x00000000.00800d00
ECC error tern 0x00000000.00000100 at addr 00100 at addr 0x00000000.00800f with addr pattern 0x00000000.000esting address line with addr0
ECC error when testing addrn testing address line with addr00000000.00804000
ECC error whenddr 0x00000000.00805000
ECC error when testing address line witECC error when testing address 000 at addr 0x00000000.00806000
.00001000 at addr 0x00000000.00807000
ECC error when testing ad000.00808000
ECC error when tes0000000.00001000 at addr 0x00000ern 0x00000000.00001000 at addr 0x00000000.00809000
ECC error wt addr 0x00000000.0080a000
ECC 01000 at addr 0x00000000.0080b00with addr pattern 0x00000000.000s line with addr pattern 0x00000000.00001000 at addr 0x00000000.0x000
ECC error whenddr 0x00000000.00810000
ECC error when testing address line witECC error when testing address l00 at addr 0x00000000.00820000
.00010000 at addr 0x00000000.00830000
ECC error when testing ad000.00840000
ECC error when tes0000000.00010000 at addr 0x00000h addr 0x00000000.00860000
ECC er pattern 0x00000000.00010000 atith addr pattern 0x00000000.00010000 at addr 0x00000000.0087000000.00010000 at addr 0x00000000.0 li0
ECC error when testing address line with addr pattern 0x0000g address line with addr pattern.008d0000
ECC error when testin0000000.008e0000
ECC error when testing address line with addr r(2)
ECC error when testing addddr 0x00000000.008f0000
mem_addi00000000.00900000
ECC error whrn 0x00000000.00100000 at addr 0x pattern 0x00000000.00100000 at addr 0x00000000.00a00000
ECC er000 at addr 0x00000000.00b00000ith addr pattern 0x00000000.00100line with addr pattern 0x00000000.00100000 at addr 0x00000000.00000
ECC error when testing address line with addr pattern 0x0000g address line with addr pattern.01100000
ECC error when testin0000000.01200000
ECC error when testing address line with addr or when testing address line withdr 0x00000000.01300000
ECC erri0000
ECC error when testing add00100000 at addr 0x00000000.0150000000.00100000 at addr 0x00000000.01600000
ECC error when testx00000000.01700000
mem_addr(2)
rn 0x00000000.00100000 at addr 0line with addr pattern 0x00000000.01000000 at addr 0x00000000.0000000000.01000000 at addr 0x00
ECC error when testing addres05800000
ECC error when testing address line with addr pattern testing address line with addr p000000.06800000
ECC error when C error when testing address li0 at addr 0x00000000.08800000
EC1000000 at addr 0x00000000.09800000
ECC error when testing addr0.0a800000
ECC error when testi00000.01000000 at addr 0x0000000n 0x00000000.01000000 at addr 0x00000000.0b800000
ECC error wheaddr 0x00000000.0c800000
.01000000 at addr 0x00000000.0eline with addr pattern 0x00000000dress line with addr pattern 0x00000000.01000000 at addr 0x00000ith addrw
ECC error when testing address line with addr pattern 0x000000Slot 1
Start Addr: 0x000000000800000
Info : 512MB at Dimm ank: 1 pa=0x00000000.40000000 size=0x20000000
mem_addr(1): UE
mem_addr(2)
ECC error whenddr 0x00000000.40000000
ECC erroattern 0x00000000.00000010 at aE addr pattern 0x00000000.00000010 at addr 0x00000000.40000010
.00000010 at addr 0x00000000.4000ne with addr pattern 0x000000000ress line with addr pattern 0x00000000.00000010 at addr 0x00000ern 0x00w
ECC error when testing address line with addr pattern 0x000000address line with addr pattern 0x000070
ECC error when testing t0000.40000080
ECC error when testing address line with addr pa when testing address line with a 0x00000000.40000090
ECC errore witECC error when testing address l10 at addr 0x00000000.400000b0
.00000010 at addr 0x00000000.400000c0
ECC error when testing ad000.400000d0
ECC error when test000000.00000010 at addr 0x00000ern 0x00000000.00000010 at addr 0x00000000.400000e0
ECC error wt addr 0x00000000.400000f0
mem_ar pattern 0x00000000.00000010 a0tern 0x00000000.00000100 at addrsting address line with addr patwhen testing address line with addr0
ECC error when testing address line with addr pattern 0x0000g address line with addr pattern 40000400
ECC error when testinpr when testing address line withdr 0x00000000.40000600
ECC erron at addr 0x00000000.40000700
ECC error when testing address li0800
ECC error when testing add00000100 at addr 0x00000000.4000000000.00000100 at addr 0x00000000.40000900
ECC error when testx00000000.40000a00
ECC error whrn 0x00000000.00000100 at addr 0r100 at addr 0x00000000.40000c00
th addr pattern 0x00000000.00000line with addr pattern 0x000)
ECC error when testing addres0esting address line with addr p000000.40001000
ECC error when tr 0x00000000.40002000
ECC error when testing address line with C error when testing address lin at addr 0x00000000.40003000
EC0001000 at addr 0x00000000.40004000
ECC error when testing addr0.40005000
ECC error when testi00000.00001000 at addr 0x0000000nddr 0x00000000.40007000
ECC er pattern 0x00000000.00001000 at ah addr pattern 0x00000000.00001000 at addr 0x00000000.40008000
.00001000 at addr 0x00000000.40line with addr pattern 0x00000000dress line with addr pattern 0x00000000.00001000 at addr 0x00000ern 0x000
ECC error when testing address line with addr pattern 0x00000 address line with addr pattern 4000e000
ECC error when testing000000.4000f000
mem_addr(2)
ECC error when testing address lin000
ECC error when testing addre010000 at addr 0x00000000.40000n0000000.40020000
ECC error when 0x00000000.00010000 at addr 0x0pattern 0x00000000.00010000 at addr 0x00000000.40030000
ECC err00 at addr 0x00000000.40040000
h addr pattern 0x00000000.000100ine with addr pattern 0x00000000.00010000 at addr 0x00000000.4000000000.00010000 at addr 0x00000dress li0
ECC error when testing address00a0000
ECC error when testing address line with addr pattern 0esting address line with addr pa00000.400b0000
ECC error when ta error when testing address lin at addr 0x00000000.400d0000
ECC010000 at addr 0x00000000.400e0000
ECC error when testing addre.400f0000
mem_addr(2)
ECC erro0000.00010000 at addr 0x00000000 addr pattern 0x00000000.00100000 at addr 0x00000000.40000000
ECC error when testing address line with addr pattern 0x00000000.0n 0x00000000.00100000 at addr 0ing address line with addr pattern testi
ddress line with addr pattern 0x600000
ECC error when testing a0000.40700000
ECC error when testing address line with addr pa0when testing address line withCC error when testing address lin at addr 0x00000000.40900
Er0100000 at addr 0x00000000.40a00000
ECC error when testing add00.40b00000
ECC error when testi00000.00100000 at addr 0x000000en 0x00000000.00100000 at addr 0x00000000.40c00000
ECC error wh addr 0x00000000.40d00000
ECC errpattern 0x00000000.00100000 at
0.00100000 at addr 0x00000000.40fine with addr pattern 0x0000000hen testing address line with addr 0
ECC error when testing address line with addr pattern 0x00000 address line with addr pattern 02000000
ECC error when testinga when testing address line with a 0x00000000.44000000
ECC error at addr 0x00000000.45000000
ECC error when testing address lin000
ECC error when testing addre000000 at addr 0x00000000.46000n0000.01000000 at addr 0x00000000.47000000
ECC error when testi00000000.48000000
ECC error when 0x00000000.01000000 at addr 0xr00 at addr 0x00000000.4a000000
h addr pattern 0x00000000.010000ine with addr pattern 0x00000000.01000000 at addr 0x00000000.4b00000000.01000000 at addr 0x000000ress lit
mem_addr(2)
ECC error when te 0x00000000.40000000
ECC error when testing address line with anfo : 512MB at Dimm Slot 2
Stat addr 0x00000000.50000000
Iize: 512 MBytes
bank: 2 pa=0x00000000.80000000 size=0x2000.20000000
ecc = TRUE
mem_addr(0000.80000000, size = 0x00000000 0x00000000.00000010 at addr 0x0g address line with addr pattern testing address line with addr0
ECC error when testing adeen testing address line with addx00000000.80000060
ECC error wh addr 0x00000000.80000070
ECC error when testing address line w
ECC error when testing address0010 at addr 0x00000000.8000008000.00000010 at addr 0x00000000.80000090
ECC error when testing 00000.800000a0
ECC error when tx00000000.00000010 at addr 0x000 at addr 0x00000000.800000c0
ECaddr pattern 0x00000000.00000010 with addr pattern 0x00000000.00000010 at addr 0x00000000.8000000000.00000010 at addr 0x00000000ss li0
ECC error when testi00000000.80000200
ECC error when testing address line with addrror when testing address line w addr 0x00000000.80000300
ECC er100 at addr 0x00000000.80000400
ECC error when testing address 000500
ECC error when testing a0.00000100 at addr 0x00000000.8000000000.00000100 at addr 0x00000000.80000600
ECC error when te 0x00000000.80000700
ECC error at addr 0x00000000.80000800
ECCddr pattern 0x00000000.00000100 with addr pattern 0x00000000.00000100 at addr 0x00000000.8000090000.00000100 at addr 0x00000000ss li0
ECC error when testing address line with addr pattern 0x00ror when testing address line wi00.80000f00
mem_addr(2)
ECC er000 at addr 0x00000000.80000000
ECC error when testing address 001000
ECC error when testing a0.00001000 at addr 0x00000000.80s0x00000000.80003000
ECC error wern 0x00000000.00001000 at addr dr pattern 0x00000000.00001000 at addr 0x00000000.80004000
ECC 01000 at addr 0x00000000.8000500with addr pattern 0x00000000.000s line with addr pattern 0x00000000.00001000 at addr 0x00000000.0x000
ECC error when testing addr0.8000b000
ECC error when testing address line with addr pattern testing address line with addr00000000.8000c000
ECC error whetECC error when testing address 000 at addr 0x00000000.8000e000
.00001000 at addr 0x00000000.8000f000
mem_addr(2)
ECC error wh addr 0x00000000.80000000
ECC dr pattern 0x00000000.00010000 atith addr pattern 0x00000000.00010000 at addr 0x00000000.8001000000.00010000 at addr 0x00000000.8 li0
ECC error when testing addr0.80070000
ECC error when testing address line with addr patteen testing address line with addr 0000000.80080000
ECC error when testing address l00 at addr 0x00000000.800a0000
0.00010000 at addr 0x00000000.800b0000
ECC error when testing a0000.800c0000
ECC error when tes0000000.00010000 at addr 0x0000wern 0x00000000.00010000 at addr 0x00000000.800d0000
ECC error at addr 0x00000000.800e0000
ECC dr pattern 0x00000000.00010000 0ttern 0x00000000.00100000 at addrsting address line with addr pa when testing address line with addr0
ECC error when testing address line with addr pattern 0x000ng address line with addr pattern.80300000
ECC error when testi or when testing address line witddr 0x00000000.80500000
ECC err00 at addr 0x00000000.80600000
ECC error when testing address l00000
ECC error when testing add00100000 at addr 0x00000000.8070000000.00100000 at addr 0x00000000.80800000
ECC error when tes0x00000000.80900000
ECC error whrn 0x00000000.00100000 at addr e0000 at addr 0x00000000.80b00000ith addr pattern 0x00000000.0010 line with addr pattern 0x000
ECC error when dr 0x00000000.81000000
ECC error when testing address line withCC error when testing address l00 at addr 0x00000000.82000000
E01000000 at addr 0x00000000.83000000
ECC error when testing add00.84000000
ECC error when tes0000000.01000000 at addr 0x000000rn 0x00000000.01000000 at addr 0x00000000.85000000
ECC error wh addr 0x00000000.86000000
ECC 00000 at addr 0x00000000.87000000ith addr pattern 0x00000000.0108 line with addr pattern 0x00000000.01000000 at addr 0x00000000.0x000
ECC error when testing addr0.8d000000
ECC error when testing address line with addr pattern testing address line with addr 0000000.8e000000
ECC error whedddr 0x00000000.8f000000
mem_addr(2)
ECC error when testing ad000.80000000
ECC error when test000000.10000000 at addr 0x000002MBytes
bank: 3 pa=0x000000 0x00000000.c0000000 Size: 512 m_addr(1): addr = 0x00000000.c0000000, size = 0x00000000.2000000wi0
ECC error when testing address line with addr pattern 0x00000 address line with addr pattern 00000010
ECC error when testinga when testing address line with r 0x00000000.c0000030
ECC error at addr 0x00000000.c0000040
ECC error when testing address lin050
ECC error when testing addr0000010 at addr 0x00000000.c000000000.00000010 at addr 0x00000000.c0000060
ECC error when testi00000000.c0000070
ECC error when 0x00000000.00000010 at addr 0xr10 at addr 0x00000000.c0000090
h addr pattern 0x00000000.000000ine with addr pattern 0x00000000.00000010 at addr 0x00000000.c000000000.00000010 at addr 0x00000dress li0
mem_addr(2)
ECC error when testing address line with addrror when testing address line witddr 0x00000000.c0000000
ECC er100 at addr 0x00000000.c0000100
ECC error when testing address 000200
ECC error when testing ad.00000100 at addr 0x00000000.c0s0x00000000.c0000400
ECC error wern 0x00000000.00000100 at addr dr pattern 0x00000000.00000100 at addr 0x00000000.c0000500
ECC 00100 at addr 0x00000000.c000060with addr pattern 0x00000000.000s line with addr pattern 0x00000000.00000100 at addr 0x00000000.0x000
ECC error when testing addr0.c0000c00
ECC error when testing address line with addr pattern testing address line with addr 0000000.c0000d00
ECC error whetmem_addr(2)
ECC error when test00 at addr 0x00000000.c0000f00
rn 0x00000000.00001000 at addr 0x00000000.c0000000
ECC error wh addr 0x00000000.c0001000
ECC er pattern 0x00000000.00001000 atith addr pattern 0x00000000.00001000 at addr 0x00000000.c000200000.00001000 at addr 0x00000000.c li0
ECC error when testing address line with addr pattern 0x0000g address line with addr pattern.c0008000
ECC error when testinpr when testing address line witddr 0x00000000.c000a000
ECC erro0 at addr 0x00000000.c000b000
ECC error when testing address lic000
ECC error when testing add00001000 at addr 0x00000000.c000000000.00001000 at addr 0x00000000.c000d000
ECC error when testx00000000.c000e000
ECC error whrn 0x00000000.00001000 at addr 0d0000000.00010000 at addr 0x0000ddress line with addr pattern 0x0ting address line with addr0
ECC error when testing addresc0040000
ECC error when testing address line with addr pattern testing address line with addr or when testing address line withdr 0x00000000.c0060
ECC erri0 at addr 0x00000000.c0070000
ECC error when testing address l80000
ECC error when testing add00010000 at addr 0x00000000.c00t000000.00010000 at addr 0x00000000.c0090000
ECC error when tes0x00000000.c00a0000
ECC error whrn 0x00000000.00010000 at addr e0000 at addr 0x00000000.c00c0000
th addr pattern 0x00000000.0001 line with addr pattern 0x000)
ECC error when testing addre testing address line with addr pa00000.c0100000
ECC error when dr 0x00000000.c0200000
ECC error when testing address line withCC error when testing address lin at addr 0x00000000.c0300000
Er0100000 at addr 0x00000000.c0400000
ECC error when testing add00.c0500000
ECC error when testi00000.00100000 at addr 0x000000eaddr 0x00000000.c0700000
ECC er pattern 0x00000000.00100000 at th addr pattern 0x00000000.00100000 at addr 0x00000000.c0800000
0.00100000 at addr 0x00000000.c09in0
ECC error when testing address line with addr pattern 0x00000 address line with addr pattern c0e00000
ECC error when testing000000.c0f00000
mem_addr(2)
ECC error when testing address lin000
ECC error when testing addre000000 at addr 0x00000000.c0000n0000000.c2000000
ECC error when 0x00000000.01000000 at addr 0x0pattern 0x00000000.01000000 at addr 0x00000000.c3000000
ECC err00 at addr 0x00000000.c4000000
h addr pattern 0x00000000.010000ine with addr pattern 0x00000000.01000000 at addr 0x00000000.c500000000.01000000 at addr 0x00000dress li0
ECC error when testing addressa000000
ECC error when testing address line with addr pattern 0esting address line with addr pa00000.cb000000
ECC error when ta error when testing address lin at addr 0x00000000.cd000000
ECC000000 at addr 0x00000000.ce000000
ECC error when testing addre.cf000000
mem_addr(2)
ECC erro0000.01000000 at addr 0x00000000 addr pattern 0x00000000.10000000 at addr 0x00000000.c0000000
E10000000 at addr 0x00000000.d000ne with addr pattern 0x00000000.z0x00000000.1f800000 ecc=1
PST: addr=0x00000000.00800000 size=U MODULE upa_config is 0x0000003a.00000000
ecc=TRUE, MC0 = 0x......00.96a0cf86
Write 0xa5a5a5a5.a5a5a5a5 ...............................................................................................................
Read ....................................................................................................................................
Write 0x96969696.96969696 ...............................................................................................................
Read ....................................................................................................................................
Write 0xbbbbbbbb.bbbbbbbb ...............................................................................................................
Read ....................................................................................................................................
Write 0xdddddddd.dddddddd ...............................................................................................................
Read ....................................................................................................................................
Info : 512MB at Dimm Slot 1
Start Addr: 0x000000.40000000 size=0x00000000.es
mem_check_blk(1): addr=0x00x00000000.00000016
CPU MODULE upa_config is 0x0000003a.00000000a5 ...............= 0x00000000.96a0cf86
Write 0xa5a5a5a5.a5a5a5.5 ...............................................................................................................
Read ....................................................................................................................................
Write 0x96969696.96969696 ...............................................................................................................
Read ....................................................................................................................................
Write 0xbbbbbbbb.bbbbbbbb ...............................................................................................................
Read ....................................................................................................................................
Write 0xdddddddd.dddddddd ...............................................................................................................
Read ...................................................................................................................................s
2
Start Addr: 0x00000000.800000 size=0x00000000.20000000 ecc=1
PSTATE reg = 0x00000.800UE, MC0 = 0x00000000.96a0config is 0x0000003a.00000000
ecc=TR.........................cf86
Write 0xa5a5a5a5.a5a5a5a5 ...............................................................................................................
Read ....................................................................................................................................
Write 0x96969696.96969696 ...............................................................................................................
Read ....................................................................................................................................
Write 0xbbbbbbbb.bbbbbbbb ...............................................................................................................
Read ....................................................................................................................................
Write 0xdddddddd.dddddddd ...............................................................................................................
Read ....................................................................................................................................
Info : 512MB at Dimm Slot 3
blk(1): addr=0x00000000.c000000000 Size: 512 MBytes
mem_check_1
PSTATE reg = 0x00000000.00000016
CPU MODULE upa_config is 0x0xa5a5a5a5.a5a5a5a5 ......RUE, MC0 = 0x00000000.96a0cf86
Write .........5.a5a5a5a5 ...............................................................................................................
Read ....................................................................................................................................
Write 0x96969696.96969696 ...............................................................................................................
Read ....................................................................................................................................
Write 0xbbbbbbbb.bbbbbbbb ...............................................................................................................
Read ....................................................................................................................................
Write 0xdddddddd.dddddddd ...............................................................................................................
Read ...................................................................................................................................[
Status of this POST run: PASS
diag-script=none
Ti
Power On Selftest Complmonth/date year] 07/03 1968
.0000.0000 ffff.ffff.f00b.63f0 0002.3333.0200.001 = 0000.0000umper is set to 0000.0000.0000.000a
Software Po01b
Speed JBP 4.17.1 2005/04/11 14:31
CPU SPEED 0x0000.0000.26be.3680
Initializing Memory Controller PU SPEED 0x0000.0000.26be.3680
Initializing Memory Controller
M000.cf00.0000.76a0.cf04
MCR1 0000.0000.8000.8000
MCR2 0000.0000.cfff.eeee
MCR3 0000.0000.0060.47ff
Clearing E$ Tags Done
Clearing I/D TLBs Done
Probing Memory Done
Clearing Memory Done
MEM BASE = 0000.0000.c000.0000
MEM SIZE = 0000.0000.2000.0000
MMUs ON
Find dropin, Copying one, Size 0000.0000.0000.3b50
PC = 0000.01ff.f000.2dc4
PC = 0000.0000.0000.2e08
Find dropin, (copied), Decompressing Done, Size 0000.0000.0006.0a10
ttya initialized
Reset Control: BXIR:0 BPOR:0 SXIR:0 SPOR:1 POR:0
/: upa at 1f,0 pci
/: upa at 0,0 SUNW,UltraSPARC-IIe (512 KB)
Loading Support Packages: obp-tftp kbd-translator
Lo idprom
/pci@rivers: ebus
/pci@1f,0/ebus@c: flashprom eepromerial serial
/pci@1f,0/isa@7/dma@0,0ci@1f,0/isa@7: dma power sf,0: Device 3 pmu
/pci@1f,0/pmu@3: i2c beep ppm fan-control @1pd dimm-spd dimm-spd ,0: temperature card-reader dimm-spd dimm-spd dimm-spd dimm-spd
: temperature card-reader dimm-spd dimm-spd dimm-spd dimm-spd
/meory Bank #ing Memory Bank #0 512 Megabytes
/memory: Probing Memegabytes
/memory: Probing Memorry: Probing Memory Bank #2 512 Megabytes
/memory: Probing Memory Bank #3 512 Megabytes
/pci@1f,0: Device c network firewire usb
/pci@1f,0: Device 8 sound
/pci@1f,0: Device d ide disk cdrom
e
/pci@1f,0/pci@5: pci
/pci@1f,0/pci@5: Device 0 Nothing therice 2 Nothing there
evice 1 Nothing there
/pci@1f,0/pci@5: Device 2 Nothing there
/pci@1f,0: Device 13 SUNW,m64B
Reset Control: BXIR:0 BPOR:0 SXIR:0 SPOR:1 POR:0
/: upa at 1f,0 t Packages: obp-tftp kbd-translaARC-IIe (512 KB)
Loading Suppor ebus
/pci@1f,0/ebus@c: flashprom eeprom idprom
/pci@1f,0: D,0/isa@7/dma@0,0: floppy parallema power serial serial
/pci@1fci@1f,0/pmu@3: i2c beep ppm fan-control
/pci@1f,0/pmu@3/i2c@0,
1@1f,0: Device c network firewiremory Bank #3 512 Megabytesmm-spd dimm-spd dimm-spd
/pci
/pci@1f,0: Device d ide disk cdrom
/pci@1f,0: Device 5 pci ce 1 Nothing there
/pci@1f,0/phing there
/pci@1f,0/pci@5: Devii@1f,0: Device 13 SUNW,m64B
Sun Blade 150 (UltraSPARC-pcll rights reserved.
OpenBootight 2005 Sun Microsystems, Inc. ASerial #13169831.
Boot device: net File and args:
Using Onboard Transceiver - Link Up.
Requesting Internet Address for 8:0:20:c8:f4:a7
Requesting Internet Address for 8:0:20:c8:f4:a7
Requesting Internet Address for 8:0:20:c8:f4:a7
Requesting Internet Address for 8:0:20:c8:f4:a7
Requesting Internet Address for 8:0:20:c8:f4:a7
Requesting Internet Address for 8:0:20:c8:f4:a7
Requesting Internet Address for 8:0:20:c8:f4:a7
Requesting Internet Address for 8:0:20:c8:f4:a7
Requesting Internet Address for 8:0:20:c8:f4:a7
Requesting Internet Address for 8:0:20:c8:f4:a7
Requesting Internet Address for 8:0:20:c8:f4:a7
Requesting Internet Address for 8:0:20:c8:f4:a7
>> OpenBSD BOOT 1.7
Trying bsd...
